This invention relates generally to a process for fabricating semiconductor devices and more specifically to a process for forming LDD NMOS and CMOS devices.
MOS transistors with channel lengths of 1.5 microns or less are prone to a well documented problem known as hot carrier injection. The problem occurs as a result of a large electric field developed in the substrate near the drain region when the transistor is operated in a saturated condition. The large electric field at the drain edge provides sufficient potential to force carriers into the transistor gate dielectric. The injected carriers increase the amount of trapped charge in the gate dielectric and change the charge distribution causing a shift in the threshold voltage. The problem is much more severe in n-channel transistors than in p-channel transistors because of the high electron mobility and the surface channel aspect of the NMOS transistor. Over a period of time the amount of trapped charge in the gate dielectric increases as the transistor is repeatedly brought to a condition of saturation. Eventually, the threshold is shifted to a point where the transistor can no longer be controlled by applying voltage to the gate electrode, and the circuit fails.
One solution to the problem of carrier injection is to form a lightly-doped drain (LDD) structure. The LDD structure consists of lightly-doped source/drain regions adjacent to the gate with heavily-doped source/drain regions laterally displaced from the gate electrode. The lightly-doped region is diffused just under the gate dielectric and produces a smaller electric field near the drain edge, thus reducing carrier injection into the dielectric. The heavily-doped source/drain region provides a low resistance region where an ohmic contact can be made.
In order to be manufactured in an efficient manner it is necessary that the process of forming the LDD structure be compatible with the self-aligned transistor gate fabrication technique. To achieve this compatibility, sidewall spacers are formed on the side of the gate to space the heavily-doped source/drain regions a prescribed distance away from gate electrode without using a critical photolithographic alignment step. The process typically involves lightly implanting the active region through an overlying dielectric layer using the gate as a hard mask. The sidewall spacer is formed by depositing a conformal layer of sidewall spacer forming material overlying the gate electrode. The sidewall spacers are formed by anisotropically etching the spacer forming material to leave the material on all vertical edges including the edges of the gate electrodes. The spacers thus formed are used as an ion implantation mask to displace the heavily-doped region a distance away from the gate electrode with the lateral distance being determined by the deposited thickness of the spacer forming material.
Various approaches to the LDD formation process have appeared in the prior art. For the most part these methods have been directed to reducing the number of photomasking steps required to form the structure in a CMOS process. The prior mask reduction methods usually employ an additional oxidation step. For example, Solo(de Zaldivar) in U.S. Pat. No. 4,420,872, oxidizes the polysilicon gate electrode to form a sidewall spacer. This process has the disadvantage of enlarging the thickness of the gate dielectric layer near the edge of the gate electrode. The encroachment of the sidewall spacer under the gate shortens the gate electrical field and disrupts the alignment of the source/drain regions with the gate edge.
Another mask reduction technique described by Parrillo et al, in U.S. Pat. No. 4,753,898 reverses the order of the implant steps in a CMOS process by first forming a heavily-doped NMOS source/drain region, then uses the heavily-doped layer to enhance the growth of a protective oxide over the source/drain. The thick oxide protects the NMOS source/drain from the implant used to form the source/drain region for the PMOS transistor. This method can induce the problem of an unwanted redistribution of impurity atoms during the oxidation process. The diffusion of impurity atoms away from the surface of the silicon substrate reduces the surface concentration of the impurity thus compromising the formation of the necessary ohmic contact to the source/drain region.
The methods described above are also characteristic of LDD formation methods that use a sidewall spacer forming material which must be anisotropically etched by a gaseous plasma mixture of reactive chemical agents. The spacer forming material is typically a deposited silicon dioxide, silicon nitride, or polycrystalline silicon (polysilicon). The chemical agents used in the prior art to etch films of this type comprise compounds of halogenated hydrocarbons, molecular halogens such as fluorine and chlorine, and hydrogenated halogens. These agents are used singularly or in varying combinations to anisotropically etch the spacer forming materials previously described. One problem with this technique is that these etchants used to form the sidewall spacer will also attack single crystal silicon in the source/drain areas of the substrate during the etching of the spacer forming material.
Typically the etching of the spacer forming material is carried out for a period of time longer than that which is necessary to just remove the spacer material from all horizontally disposed surface. This is known as an overetch, or overetching, and is commonly employed to completely remove spacer forming material from areas of the substrate having high topographical contrast. The complete removal of excess material is necessary to avoid unwanted masking of the ion implant used to form the heavily-doped source/drain region.
The problem of etchant attack in the source/drain areas can also occur during the process of removing the sidewall spacers prior to further processing of an MOS device. In this instance, an isotropic etch is performed that etches in all directions at the same rate. The same chemical agents described previously are again used for the isotropic etch. The surface of the source/drain region is exposed for the entire duration of this etch process providing ample opportunity for the etchants to pit the surface.
The etchants penetrate the dielectric layer overlying the source/drain region and attack the silicon substrate during the process of overetching the spacer forming material, and etching to remove the spacer after formation of the lightly-doped drain. The attack on the silicon often occurs because the gasses selected to etch the spacer forming material also react with, and etch, the underlying dielectric material at nearly the same rate. This is known in the art as a non-selective etch. The selectivity of an anisotropic reactive ion etch is determined by the ratio of the etch rate of the material to be etched to that of the underlying material. The reactive gasses selected for the reactive ion etch used to form a sidewall spacer must yield as high of etch selectivity as possible with respect to the underlying dielectric layer. In the case of anisotropically etching a spacer forming material such as silicon dioxide, obtaining high selectivity to an underlying dielectric material (often thermally grown silicon dioxide) is extremely difficult.
The scaling of circuit dimensions to smaller values has resulted in a progressive reduction in source/drain junction depths in the silicon substrate. The reduced junction depth, 0.15 microns in the case of some high performance VLSI memory devices, makes the transistor more susceptible to defect induced performance degradation. Surface defects can thread through such shallow junctions. The penetration of the overlying dielectric layer, and the subsequent attack on the substrate during the overetch, can create substrate defects in the source/drain region. Etchant pitting of the silicon creates a rough surface and disturbs the silicon crystal lattice causing the formation of dislocations in the silicon lattice. The removal of the overlying dielectric layer exposes the surface to metal contaminants sputtered from the reactor chamber surfaces during the etch. These defects act as precipitation sites for impurities in a process known as gettering. The defects thus formed can thread through the source/drain junction causing current leakage between the source/drain region and the substrate, which is known as source/drain junction leakage. In normal transistor operation a bias voltage is applied to the substrate such that the source/drain junctions are reversed biased. This biasing condition cannot be adequately maintained if current leaks through the junction. The presents of a continuous drain current introduces drain voltage instability which leads to poor data retention in a static memory device such as an SRAM.
The fabrication of defect free transistors with LDD structures becomes increasingly important as circuit geometries are scaled to smaller dimensions. The smaller transistor gate lengths and high operating supply voltages that make LDD structures necessary demand very shallow source/drain junction depths in order to meet scaling requirements. Accordingly, a need existed for an improved process for the formation of an LDD structure using a side wall spacer forming material which can be reliably etched without causing source/drain junction leakage. A further need existed for a process with a reduced number of photomasking steps, in both an NMOS and a CMOS process, that does not compromise the integrity of the gate dielectric or the doping uniformity of the lightly and heavily-doped source/drain regions.